When announcing the Ryzen 5000, which was complemented by a stacked L3 cache, AMD already flirted with the fact that this technology would also work well in server CPUs. Rumors circulating on Twitter now indicate: Milan will be re-released as Milan X with 768 MB of L3 cache, of which 512 MB of 3D V cache.
For Ryzen 5000, 3D V-Cache is already official
It is officially known that AMD will begin production of the Ryzen 5000 processor this year, which has not only 32 MB of L3 cache per 8-core chiplet (CCD) up to date, but also 64 MB per CCD. There is 32MB + 64MB = 96MB of cache per CCD, a Ryzen 5000 with 16 cores and thus two CCDs comes out to a total of 192MB [2 × (32 MB + 64 MB)].
Milan X achieves 768 MB L3 cache with 8 CCDs
As with the Milan X, AMD appears to be using the same technology in the near future to expand the Epic series based on the Milan architecture (the chiplet I/O die approach with the Zen 3), apparently on an unchanged basis. with. On top, that is, based on a 64-core processor with 8 CCDs, 8 × (32 MB + 64 MB) = 768 MB of L3 cache is possible.
At least that’s what a generally accurate Twitter user claims executable fix and named four possible Milan-X models: the Epic 7773X, 7573X, 7473X and 7373X with 64, 32, 24 and 16 cores, respectively. The table below includes these models as well as other matching processors available now.
768 MB L3 from 16 to 64 cores
When looking at the four SKUs, it’s worth noting that all of them must use the full 768 MB L3 cache, which – if the matching X only reverses the matching architecture – only works if the 16-core Epyc 7373X Processor still available. All 8 CCDs, but only two of the eight cores per CCD are active. AMD has already followed this approach with the Milan: the F models, like the largest 8 CCD expansion stages, offer the full 256 MB as all eight CCDs can be found on the package – 64 in at the bottom of the CPU. with only 16 active cores.
It’s Behind AMD’s 3D V-Cache Technology
At a presentation of 3D-V-Cache technology at Virtual Computex in June, AMD already discussed the technology in detail. The 64 MB additional cache takes up a base area of 6 × 6 mm in the CCD, making it as large as the 32 MB L3 cache that already exists. With its two 32 MB layers, the new CCD has a triple-stacked L3 cache module with 96 MB.
The attached L3 cache is a native 64 MB chip, it still serves as a direct extension of the existing L3 cache in the CCD, requiring no software adjustments, as it has no control functions and requires Basic functionality for all units may come along. Since these already exist, AMD can accommodate 64 MB of pure SRAM in the same space as 32 MB before. Zen 3 was prepared for this possibility from the outset, and development and implementation with partner TSMC took years, AMD explained.
The stacking technology is based on TSV, as they are already used in various stacking solutions. that chipbonden Happens through direct contact of the copper layers, with no additional BGA contact surfaces or the like, as for example Intel’s approach with stacking provides.
In order to accommodate the additional L3 cache on the CCD without changing the height, the CCDs of the respective processors will be thinner in the future, so that eventually, with the additional cache, they will be as high as the I/O die and finally the heat spreader. To fit down.
